In tandem with automatic test pattern generation (ATPG) tools, scan design techniques are used to efficiently test chips using many test vectors that provide high fault coverage. In a typical scan design technique, a scan chain or multiple scan chains may be formed in a chip, such as a system-on-chip (SOC), by connecting flip-flops in the chip as one or more long shift registers when a scan mode is asserted for the chip. During the scan mode, a scan shift operation or a scan capture operation may be performed. When the scan shift operation is asserted, one or more test patterns may be loaded onto the scan chain(s). During the scan shift operation, the normal operation of the chip may be ceased. Once the loading of the test pattern(s) is completed, the scan capture operation may be asserted. During the scan capture operation, pseudo-functional operation of the chip may be performed based on functional inputs to the chip as well as the test pattern(s) loaded onto the scan chain(s). Then, the result of the scan capture operation may be shifted out during the subsequent scan shift operation, where the result may be compared with the expected pattern to verify the sound operation of the chip.
Today's SOCs have design blocks operating with different clocks and frequencies, i.e., multi-clock domains. During the chip's functional operation, the interface across the multi-clock domains are asynchronous and not timing critical. This allows the clock trees for different clocks associated with the multi-clock domains to be balanced independently. However, during the scan mode where elements of the chip are clocked by a single scan clock from a tester (e.g., an external tester), timing issues do appear. In the case of the scan-shift operation, the clock imbalance across the multi-clock domains may be solved either by isolating scan chains of the different clock domains or by using lockup latches wherever data crosses one or more of the multi-clock domains. But during the scan-capture operation, where so many data paths violate timing across the imbalanced clock trees, it may be difficult to solve the clock imbalance across the multi-clock domains.